1. Field of the Invention
The present invention relates to a semiconductor device and to a fabrication method thereof, and in particular, to a Wafer Level Chip Size Package (WCSP) and to a fabrication method thereof.
2. Related Art
Wafer level chip size packages generally adopt a structure with plural external connection terminals disposed on a chip-shaped semiconductor substrate (see Japanese Patent Application Laid-Open (JP-A) No. 2000-235979).
Conventionally, a semiconductor wafer for which pre-processing has been completed is made into individual semiconductor chips by dicing, then packaged by using, for example, bonding, a resin mold or the like. Recently, however, in order to achieve even smaller sizes and reduced thickness, the use of wafer level chip size packages is becoming prevalent, where a semiconductor wafer is diced into individual chips to form chip size packages after forming, at a wafer stage, redistribution wirings which connect between terminal pads on a semiconductor substrate surface and external connection terminals, the external connection terminals, a resin seal and the like. However, the conventional wafer level chip size packages have a problem in moisture resistance.